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   <TITLE>Working with projects</TITLE>
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<H1>
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<P>
 A project is a set of Verilog sources logically linked together. You can create/manage/open/close projects from the <TT>Project</TT> menu.
In order to start the simulation, you must include all the needed files into the project. You do not need to include non top level files 
(i.e. those ones already included with the <CODE>`include</CODE> directive).
<P>
The <TT>Project View</TT> window to the left will hold a tree with all the scopes found inside the sources and their contents. You can browse the 
contents of the project by just clicking to a symbol from the tree and a window centered on it will be popped up. 
The icon from left of each label will indicate the type of the symbol.
<P>
Note that the symbols from included files will be placed inside the tree at the position of the `include directive.
<P>
The project files must have "<TT>.vpr</TT>" extension.
<P>
After you create a new (empty) project (by choosing the <B>Project/New
Project</B> menu item), the <B>Add file toProject</B> item from the same menu
shoul become active, so you can add the files into it.<BR><A
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